AMD has published the first official test results for its EPYC Venice server processors, and the flagship 256-core EPYC 9996 beats Intel’s Xeon 6980P by 137% and Nvidia’s 88-core Vera CPU by 124% on the SPEC CPU 2026 integer test. The numbers come from a new AMD white paper and mark the first time the Zen 6 generation has shown up in published benchmarks rather than leaked slides.
What the tests show
On the SPEC CPU 2026 intrate benchmark, the EPYC 9996 ran 2.37 times faster than Intel’s 128-core Xeon 6980P and 2.24 times faster than Nvidia’s Vera, the CPU half of the platform Nvidia pairs with its Grace architecture for AI systems. AMD also cited workload results against the same Xeon part: up to 3.7 times the NGINX web serving throughput, 3.5 times on MongoDB, 3.4 times on TPCx-AI, and 3.1 times on the GROMACS and NAMD molecular dynamics suites.
The company frames the comparisons two ways. Per-socket, the 256-core part simply has twice the cores of the Xeon 6980P. Rack-level, AMD modeled a 100-kilowatt constraint comparing two-socket systems and still claims leadership across a six-workload geometric mean that includes Java, Redis, Memcached, and TPROC-C.
The caveat that matters
These are AMD’s own numbers, run on AMD test systems, and the rack-scale comparisons are modeled estimates rather than measurements of physical racks packed with Venice and Vera hardware. AMD describes the figures as estimates based on benchmark data and system-level assumptions. Independent third-party results are expected in the fourth quarter, when Venice ships on the SP7 platform.
The pattern is familiar. Intel faced the same skepticism when it published Xeon benchmarks against AMD parts, and independent testing usually lands somewhere between the vendor’s claim and the competitor’s rebuttal. The 2.37x figure will shrink under independent methodology, but few analysts expect the direction to flip.
Why Nvidia is in the argument
The inclusion of Vera is the notable part. Server CPU competition used to be a two-company race between AMD and Intel. Nvidia’s data center push has put its own CPU silicon in the conversation, and AMD’s white paper goes out of its way to benchmark against it. An earlier version of AMD’s agentic AI benchmarks drew pushback from Nvidia, and the revised paper doubles down with the SPEC results.
For data center buyers, the stakes are concrete. Venice is the first x86 server CPU built on TSMC’s 2nm process, with up to 256 Zen 6c cores, 16-channel DDR5 at 1.6 terabytes per second, PCIe Gen 6, and CXL 3.1 on the SP7 socket. The flagship carries 1,024 MB of L3 cache and 203 billion transistors, the highest core count x86 has ever shipped. AMD claims over 70% higher performance and efficiency than the current Turin generation.
What ships when
The EPYC 9996 is the only named SKU at launch, with the full Venice lineup due in the fourth quarter. A second platform, SP8, follows in the first half of 2027 for mainstream and GPU-dense deployments with 8 to 128 cores. Intel’s answer, Xeon 6+ with up to 288 cores on its 18A process, is expected next year, which sets up the first server CPU generation where both vendors offer more than 250 cores on a socket.
Nvidia, for its part, has been shipping Vera with its Rubin platform and has not published SPEC results of its own against Venice. The comparison war will play out in customer evaluations over the next two quarters, where cloud providers run their actual workloads rather than vendor-selected ones.
For now, the message AMD wants the market to hear is simple: the CPU still matters in AI data centers, and the company that owns the x86 socket wants to keep it that way while the GPU vendors circle.
The memory problem in the background
One constraint hangs over every server CPU roadmap this year. Intel chief executive Lip-Bu Tan said at the AI Infrastructure Summit on September 15 that memory chip prices have risen roughly sevenfold and that he sees no relief until 2028. DDR5 shortage economics now shape how many channels vendors advertise and how much memory platforms can economically populate. Venice 16-channel design and 1.6 terabytes per second of bandwidth are aimed directly at workloads that stall on memory, but the DIMMs to fill them cost more every month.
AMD benchmarks for the MongoDB comparison used fully populated DDR5-6400 configurations, which is the optimistic case. Buyers quoting systems this quarter will price memory as a bigger share of the build than at any point in the DDR5 era, and some will trade down core counts to afford capacity.
The agentic AI framing is the other piece of AMD pitch. The white paper includes pipeline benchmarks where the EPYC 9996 posts a geomean throughput of 6.05 million versus 2.28 million for the Xeon 6980P, workloads AMD says represent the CPU-side stages of agentic AI systems: retrieval, tool orchestration, and preprocessing around GPU inference. Whether cloud architects buy that framing or treat the CPU as commodity plumbing around accelerators will decide how much of the Venice story lands.
Qualcomm made the same argument from the other direction at Snapdragon Summit this week, putting 30-billion-parameter models on phones. The compute industry is betting on intelligence at every tier of the stack, from 300-watt server sockets to 3-watt phone chips, and each tier wants a bigger share of the bill of materials. Venice launch quarter will collide with Intel price increases too: reports say Intel plans to raise CPU prices about 10% ahead of its March 2027 launch, which would hand AMD an opening in the renewal cycles that follow.
For the stock market, the numbers landed without drama. Intel and AMD shares both slipped earlier this month when Nvidia unveiled its own PC chip, a reminder that the market now prices CPU competition as a three-way race. The white paper changes the talking points for procurement teams, not the quarter. Shipments start in Q4, independent benchmarks follow, and the first big cloud commitments will show up in earnings calls early next year.