ASML has won commitments from TSMC, Samsung and Intel Foundry to move High NA EUV chipmaking to 12-inch photomasks, a shift meant to make the next generation of leading-edge chips cheaper to print. The Dutch toolmaker announced the industry initiative on Sept. 8, a day after signing it ahead of the SPIE BACUS conference in Monterey, California.
Photomasks are the stencils a lithography scanner uses to print circuit patterns, and the industry has used 6-inch masks for decades. High NA EUV scanners print finer features, but a single 6-inch mask cannot cover an entire field, so patterns get split and stitched back together. That stitching costs throughput. A 12-inch mask covers the full field in one pass.
The roadmap has two dates. A 12-inch mask pilot line should exist by 2031, and 12-inch High NA systems should enter advanced node production by 2033. High NA will reach production before that on 6-inch masks, which keeps the transition from blocking current tool orders.
The timing tracks AI demand. Bloomberg reported the agreements as ASML’s response to surging orders for more powerful processors. Each new accelerator generation packs in more transistors, and more layers have to be printed at the tightest tolerances lithography can deliver.
What each company committed to
| Player | Status | Timeline |
|---|---|---|
| Intel Foundry | First High NA user, over 1 million wafers processed | Volume production already underway on 6-inch masks |
| TSMC | High NA in high-volume manufacturing for advanced nodes | Starting 2030 |
| Samsung | Joined the 12-inch mask initiative | No public date |
TSMC laid out its own marker: High NA goes into high-volume manufacturing for advanced nodes starting in 2030. The foundry expects the number of layers needing High NA to grow as transistor architectures get more complex, driven by AI chip demand. Chairman and CEO C.C. Wei tied the mask transition to that work.
“We have always believed that when the industry works together to solve complex problems, we unlock possibilities that no single company could achieve alone,” said C.C. Wei, TSMC chairman and CEO.
ASML chief executive Christophe Fouquet made the same point from the supplier side, saying 12-inch masks enable greater scanner productivity and let the industry meet demand for “smaller, faster and more energy-efficient chips.” The company said High NA adopters and other major suppliers expressed interest in joining the initiative, though it did not name them.
Intel is the reference customer
Intel Foundry remains furthest along. It installed the first commercial High NA EXE system in 2024 and has since processed more than one million wafers across tool certification, R&D and volume production of select layers on Core Ultra Series 3 processors, code-named Panther Lake. ASML credited Intel with shipping the first high-volume logic product made with High NA.
Samsung’s signature matters for a different reason. The company is the leading memory maker and is pushing HBM4 output for AI accelerator customers. Advanced memory has its own printing requirements as cell structures shrink. ASML’s release did not give Samsung a timeline of its own.
The economics behind the shift
High NA machines are among the most expensive tools ever sold into chipmaking. Each one occupies its own bay, needs custom infrastructure and prints fewer wafers per hour than the older NXE scanners it complements. Productivity, not raw resolution, is where the mask change pays off.
The burden falls partly on mask suppliers. Blanks, the glass substrates under the pattern layer, come from a handful of companies, and 12-inch blanks require new production capacity. The 2031 pilot line exists partly to prove that supply chain before every fab depends on it.
The initiative lands while China’s domestic lithography push stays limited to DUV tools, which industry reporting suggests could reach high-volume production in two to five years. EUV capability there remains distant. Every node the ASML group adds extends that gap.
Cheaper leading-edge printing eventually reaches consumer devices. TSMC’s 2030 node and its successors are expected to power flagship phones, including Apple’s A-series processors. If the mask transition works as planned, the productivity gains arrive in time for those products rather than after them.
For AI chip buyers the date that counts is 2033, when 12-inch production is supposed to start. By then TSMC will have run High NA on 6-inch masks for three years, Intel longer. The mask transition is the second half of a cost curve that decides how cheap next-generation accelerators get to make.
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