IBM has unveiled what it calls the world’s first sub-1 nanometer chip technology, a 3D architecture it says packs nearly 100 billion transistors onto a chip the size of a fingernail. The catch, as with every lab breakthrough, is timing: IBM does not expect commercial production for at least five years.
The design, called nanostack, reached a 0.7nm node, also described as 7 angstroms, a unit usually reserved for measuring atoms. The current industry-standard node sits around 2nm. IBM says its prototype performed 50% better than its own 2nm chip in tests and used 70% less energy.
Node numbers have long stopped being literal measurements of transistor size. They describe a generation of manufacturing technology. Still, IBM’s claim of a working sub-1nm-equivalent design is a first, and the company says the architecture projects at least a decade of further scaling.
Building upward instead of outward
For decades the industry has followed Moore’s Law, doubling transistor counts roughly every two years. With horizontal space on a wafer nearly exhausted, chipmakers have shifted to 3D approaches that make transistors taller rather than smaller.
IBM’s nanostack takes that further than anyone else. The basic unit is two transistors stacked and bonded together, with the layers staggered to fit more transistors in the same footprint. The design also allows different material combinations in each stacked layer, so performance and power can be tuned per transistor independently of its neighbors.
Professor Alan Woodward, a computer scientist at the University of Surrey, compared the approach to building housing. Rivals such as Samsung and Intel are working on the equivalent of 30- to 50-story buildings with their own 3D chip work, he said, while IBM’s design is like proposing a 100-story skyscraper. “I think it’s fair to say IBM’s proposals are the most ambitious,” Woodward told the BBC.
Jay Gambetta, director of IBM Research and an IBM Fellow, called nanostack a landmark moment and said the company is “not just making smaller transistors” but reinventing how chips are built. At an advance media briefing he added that the technology points to a future where computing becomes more powerful without a matching rise in energy use.
Skepticism from the 2021 playbook
There is a reason for measured skepticism. When IBM debuted its 2nm chip in 2021, it claimed similar leaps in performance and energy efficiency. Five years later, those chips are still not shipping in consumer products, and production has been licensed out to foundries rather than scaled in-house.
IBM also declined to name any partners for commercializing the sub-1nm node. The company’s roadmap sees earliest adoption of nanostack technology within about five years, and most analysts expect real deployment closer to a decade.
| Generation | Transistors per fingernail-sized chip | Status |
|---|---|---|
| IBM 2nm (2021) | About 50 billion | Licensed, not in volume production |
| IBM nanostack (2026) | Nearly 100 billion | Lab validated, production in 5+ years |
Why it matters for AI
The timing is not accidental. AI data centers are consuming power at a rate that is straining grids, and chip efficiency has become the industry’s central constraint. IBM’s published results claim 50% more performance or 70% better energy efficiency than its 2nm node, and separate research presented at the VLSI 2026 conference showed a 40% scaling improvement in SRAM, the fast memory that sits next to processors.
If those numbers survive contact with manufacturing, the payoff would be large. If they do not, nanostack joins a long list of lab demos that looked better in a press release than on a production line. IBM has earned some credibility on this front, having invented the nanosheet architecture that underpins today’s leading-edge nodes, but the five-year wait will tell the real story.
The physical validation matters here. IBM demonstrated the nanostack through ultra-thin dielectric bonding in CMOS integration, dual-channel engineering, and a working CMOS inverter, which confirms the design can be physically built and supports real computation rather than existing only in simulation. That separates it from purely conceptual roadmaps.
The work was conducted at IBM’s Albany, New York research facility, which will soon host a High NA EUV lithography tool from ASML needed for printing circuits at this scale, with partners including Lam Research. The company says the tool enables the ultra-precise circuit printing that sub-1nm features demand.
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